Converter with resonant circuit elements for determing load type

ABSTRACT

The invention relates to a converter comprising resonant circuit elements (S 1,  S 2 ) for chopping a DC voltage (U 1 ), in which switch-on phases of the circuit elements (S 1,  S 2 ) are alternating, and comprising a circuit assembly ( 5 ) with resonant circuit elements (Cr, Lr) which is used for processing the chopped DC voltage (U 3 ) and for producing an output voltage (U 2 ).  
     As a type of converter load monitoring that can be changed with the least possible circuit expenditure and the least possible measuring losses, there is proposed to compare in a dead time phase (T tot ) before a circuit element is switched on the voltage (U S1 ) or (U S2 ) applied to the circuit element with a threshold (U th ) and ascertain from this comparison result whether an inductive or capacitive converter load is present.  
     As a second embodiment there is proposed to determine during a dead time phase (T tot ) the derived value (dU S1 /dt) of the voltage (U S1 ) present on the circuit element and ascertain with the determined derived value (dU S1 /dt) whether an inductive or capacitive converter load is present.

[0001] The invention relates to a converter comprising circuit elementsfor chopping a DC voltage, in which switch-on phases of the circuitelements are alternating, and comprising a circuit assembly withresonant circuit elements which is used for processing the chopped DCvoltage and for producing an output voltage.

[0002] Such load resonant converters preferably represent switchingpower supplies which are used for supplying DC voltage to a loadconnected to the output of the switching power supply. In such switchingpower supplies is first rectified an AC voltage present on the input, toobtain a converter input DC voltage. However, the invention also relatesto converters to whose inputs a DC voltage is supplied directly from aDC voltage source. Such a converter can also be used for operation ofgas discharge lamps. The converter input DC voltage is chopped by meansof a bridge circuit comprising circuit elements. The chopped DC voltageis applied to a circuit assembly with resonant circuit elements i.e.with inductive and capacitive reactance elements, so that asubstantially sinusoidal AC current flows in the circuit assembly. Atleast one inductive and at least one capacitive resonant circuit elementare to be available. To the output of the circuit assembly and thus tothe output of the converter may be connected a load. By adapting theswitching frequency, load changes and input voltage variations areadapted to. Converters with resonant circuit elements i.e. resonantconverters, enable the circuit elements to operate with high switchingfrequencies and thus relatively small-volume and light devices comparedto the possible power output can be realized. When resonant convertersare used, also a so-called zero-voltage switching operation (ZVS) isenabled with little circuit expenditure. ZVS operation is hereunderstood to mean that circuit elements are switched on (brought to theconducting state) with a lowest possible voltage of the circuit element,preferably close to zero volts. In the ZVS mode the circuit assemblywith the resonant circuit elements has an inductive input impedanceconsidered from the side of the circuit elements. In the case of a ZVSmode, MOSFET transistors are customarily used as circuit elements. Withconverters realized in this way the operation with a capacitive load isto be avoided. Such a converter mode leads to increased switching lossesand may even cause the destruction of converter circuit elements.Therefore, means are known to be provided for determining the type ofconverter load (inductive or capacitive) with such load resonantconverters.

[0003] From EP 0 430 358 A1 is known a converter circuit arrangement forgas discharge lamps in which the type of converter load is determined inthe way described above. The circuit arrangement includes a half bridgewith circuit elements for chopping a DC voltage. On the output side ofthe half bridge is arranged a circuit assembly including resonantcircuit elements, which assembly is used for supplying a voltage to adischarge lamp. Here too, operation with a capacitive converter load isto be avoided. For this reason the phase difference between the voltageapplied to the circuit assembly and the current flowing into the circuitassembly is indirectly monitored by monitoring the current flowing intothe circuit assembly.

[0004] It is an object of the invention for the converter defined in theopening paragraph to propose a further type of converter loadmonitoring, which type can be changed with the least possible circuitexpenditure and the least possible measuring losses.

[0005] The object is achieved in that in a dead time phase before acircuit element is switched on, the voltage present on the circuitelement is compared with a threshold and from the comparison resultthere is ascertained whether an inductive or capacitive converter loadis present.

[0006] Expensive measurements of phase differences are avoided in thismanner. Furthermore, only voltage measurements are necessary and nocurrent measurements linked with losses. If necessary, in case of anundesired type of converter load the normal converter operation may, forexample, be broken off and a new start sequence may be made. Determiningthe type of converter load may be effected very rapidly in this manner,so that undesired converter operating modes can be counteracted withcounter measures very rapidly. Determining the type of converter load inaccordance with the invention is also suitable for high switchingfrequencies.

[0007] In an embodiment of the invention the comparison with thethreshold takes place in each dead time phase before either of thecircuit elements is switched on. The time space up to the detection ofan undesired converter operating mode is kept smallest possible in thismanner.

[0008] The object is achieved in that, during a dead time phase, thederived value of the voltage present on a circuit element is determinedand with the aid of the determined derived value there is ascertainedwhether an inductive or a capacitive converter load is present.

[0009] Alternatively, it is possible to include a time-average value forthe derived value of the voltage present on a circuit element and usethis time-average value for the comparison. Expensive measurements ofphase differences are avoided in this manner. Furthermore, only voltagemeasurements are necessary and no current measurements linked withlosses. If necessary, in case of an undesired type of converter load thenormal converter operation may, for example, be broken off and a newstart sequence may be made. Determining the type of converter load maybe effected very rapidly in this manner, so that undesired converteroperating modes can be counteracted with counter measures very rapidly.Determining the type of converter load in accordance with the inventionis also suitable for high switching frequencies.

[0010] In an embodiment of the invention the evaluation of the derivedvalue of the voltage present on a circuit element is made for each deadtime phase and the comparison with the threshold is made before eitherof the circuit elements is switched on, i.e. the type of converter loadis monitored cycle by cycle. The time space up to the detection of anundesired converter operation mode is kept shortest possible in thismanner.

[0011] The invention also relates to an accordingly arranged controlunit, more particularly an integrated circuit for controlling at leastone of the converter circuit elements.

[0012] Examples of embodiment of the invention will be further explainedwith reference to the drawings in which:

[0013]FIG. 1 shows a block diagram for a circuit arrangement including aresonant converter,

[0014]FIG. 2 shows the circuit structure of a resonant converter inaccordance with the invention,

[0015]FIG. 3 shows timing diagrams for an inductive load,

[0016]FIG. 4 shows timing diagrams for a capacitive load,

[0017]FIG. 5 shows a block diagram of a control circuit arrangement forcontrolling circuit elements,

[0018]FIG. 6 shows a transmission function relative to the load side ofthe resonant converter,

[0019]FIG. 7 shows a flow chart in explanation of a converter operationin accordance with the invention,

[0020]FIG. 8 shows a block diagram of a second embodiment of a controlcircuit arrangement for controlling circuit elements,

[0021]FIG. 9 shows a transmission function plotted against the frequencyfor a constant load resistance for the second embodiment, and

[0022]FIG. 10 shows a flow chart in explanation of a converter operationin accordance with the second embodiment of the invention.

[0023] The block diagram shown in FIG. 1 shows a load resonantconverter—here a switching power supply—with a circuit block 1 forconverting an input DC voltage U1 into an output voltage U2—here a DCvoltage—which output voltage U2 is used for supplying power to a loadrepresented by a block 3. The input voltage U1 is generated here byrectifying an AC voltage of an AC voltage network which is the normalfashion for switching power supplies.

[0024]FIG. 2 shows in a more detailed manner the essential elements ofthe converter shown in FIG. 1. The input DC voltage U1 is here appliedto a half bridge of series-arranged circuit elements S1 and S2, whichchop the DC voltage U1. The circuit elements S1 and S2 are in thepresent case MOSFET transistors which have so-called body diodes D1 andD2 which are represented as a respective diode lying in an anti-parallelarrangement with the circuit elements S1 and S2. The circuit elements S1and S2 are controlled by a control unit 4 which for this purpose alsomeasures and evaluates the voltages U_(S1) and U_(S2) falling at thecircuit elements S1 and S2. The control unit 4 contains for each circuitelement its own control circuit, a first control circuit 10 being usedfor controlling the circuit element S1 and a second control circuit 10′for controlling the circuit element S2. The control unit 4 may berealized, for example, together with the control circuits 10 and 10′ ona single integrated circuit (IC). The control circuits 10 and 10′,however, can also be realized by means of separate ICs. By means of thecontrol unit 4 or the control circuits 10 and 10′, an automaticadaptation of the length of dead time phases is ensured, which will befurther explained in the following.

[0025] Connected in parallel to the circuit element S2 is shown acapacitor Cp at which, when the converter 1 is in operation, a choppedDC voltage U3 falls. The capacitor Cp particularly combines theparasitic capacitances of the circuit elements S1 and S2 when they arerealized as MOSFET transistors—like in the above example of embodiment.The capacitance Cp, however, may also include further additionalcapacitors. The chopped DC voltage U3 is applied to a circuit assembly5, which includes resonant circuit elements and generates an output DCvoltage U2. In the present case the circuit assembly 5 includes asresonant circuit elements a capacitance Cr and an inductance Lr whichare connected in series. Between the series combination of thecapacitance Cr and the inductance Lr and the capacitance Cp, in thedirection of the converter output, there is a rectifier arrangement 6which rectifies a current I flowing through the resonant circuitelements Cr and Lr and, as is usual, applies it to a smoothing capacitorC arranged on the output, from which the output DC voltage U2 can betapped. In FIG. 2 the output DC voltage U2 is present on a load R, whichis represented here as an ohmic resistance. Basically, the converter 1,however, could also be used for supplying an AC voltage instead of a DCvoltage. In a case like that a rectification by a rectifier arrangementand a smoothing capacitor would not be necessary and the output voltagewould be equal to the falling AC voltage at the rectifier arrangement 6of the embodiment shown in FIG. 2.

[0026] The input DC voltage U1 is converted into the chopped DC voltageU3 by alternately switching the circuit elements S1 and S2 on (bringinginto the conducting state) and off (bringing into the non-conductingstate). If the switch S1 is on, the switch S2 is off. If the switch S2is on, the switch S1 is off. Between the end of an on-phase of theswitch S1 and the beginning of the on-phase of switch S2, there isalways a dead time phase in which the two circuit elements S1 and S2 areoff. Between an end of an “on” phase of the circuit element S2 and thebeginning of the next “on” phase of the circuit element S1 there isalways such a dead time phase. Providing such dead time phases enablesZVS operation (ZeroVoltage Switching). The length of the “on” and “off”time phases of the circuit elements S1 and S2 is then adjusted by meansof the control unit 4, which will be further explained with reference toFIGS. 5 and 8. By adapting the switching frequency, a constant outputvoltage is ensured even with load variations and variations of the inputvoltage.

[0027] The top diagram of the three shown in FIG. 3 represents thedifference |U_(G1)|−|U_(G2)| of the value of the control voltage U_(G1)present on the circuit element S1 and of the value of the controlvoltage U_(G2) present on the circuit element S2. The control voltagesused as control signals for controlling the circuit elements S1 and S2represent respective gate voltages of the MOSFET transistors. If theplotted difference of the values of the control voltages equals zero,there is a dead time phase which is referred to as T_(tot). If thecircuit element S1 is set to the “on” state because a suitable controlvoltage U_(G1) is applied to the control input of the circuit elementS1, there are time spaces referred to as T_(on)(S1). In these timespaces the control voltage U_(G2) equals zero and thus the circuitelement S2 is switched off. The time spaces in which the circuit elementS2 is “on” and the circuit element S1 is “off”, are referred to asT_(on)(S2). During these time spaces the control input of the circuitelement S2 is supplied with a non-zero control voltage U_(G2), whichcauses the circuit element S2 to be switched on. Within these timespaces, the control voltage U_(G1) is equal to zero. The middle diagramin FIG. 3, shows the waveform as a function of time of the currentflowing through the resonant circuit elements Cr and Lr. Finally, in thebottom diagram of FIG. 3 is shown the waveform as a function of time ofthe voltage U3 applied to the parasitic capacitance Cp. The time axes ofthe three diagrams with the time t shown have all the same scale.

[0028] In the following is explained by way of example the changebetween the on and off-states of the circuit elements S1 and S2 withrespect to which states the operations during a switch between therespective switching cycles are elucidated. At the instant t0 thecontrol voltage U_(G2) is set to zero to cause the circuit element S2 tobe switched “off”. This leads to a discharge operation on the gateelectrode of the MOSFET transistor used for realizing the circuitelement S1. Until this discharging operation has ended, however, thecircuit element S2 is still conducting, so that the negative currentcontinues to flow through the circuit element S2 at this instant. Frominstant t1 onwards the circuit element S2 is finally switched off, sothat current can no longer flow through it. The current I flowing onbecause of the energy stored in the inductance Lr now causes frominstant t1 onwards the capacitance Cp to be charged and thus the voltageU3 to rise. At the instant t2 the voltage U3 has finally reached thevalue of the input DC voltage U1, so that the diode D1 starts beingconductive. From this instant onwards it is ensured that the circuitelement S1 is switched on with a switching voltage U_(S1) of about 0volts (ZVS with the diode forward voltage). Shortly after the instantt2—at the instant t4—the circuit element S1 is switched on because arespective control voltage U_(G2) is applied thereto. Thus a time spaceT_(on)(S1) is commenced with a circuit element S1 that is switched onand a circuit element S2 that is switched off.

[0029] At the instant t5 this time space T_(on)(S1) is ended in that thecontrol voltage U_(G1) is set to zero. This in turn leads to a dischargeoperation on the gate electrode of the MOSFET transistor used forrealizing the circuit element S1. At the instant t6 this dischargeoperation has been terminated so far that the circuit element S1 startsblocking, that is, goes to the off-state, so that the current I positiveat this instant leads to discharging the capacitance Cp and thus to afalling voltage U3. At the instant t7 the voltage U3 has reached thezero value, so that from this instant onwards the diode D2 starts beingconductive and the circuit element S2 can be switched on with aswitching voltage U_(S2) of about 0 volts (with the diode forwardvoltage), which really occurs at instant t9, shortly afterwards, after arespective control voltage U_(G2) has been applied. From this instantonwards a time space T_(on)(S2) begins, in which the circuit element S2is switched on and the circuit element S1 is switched off.

[0030] Both between the instants t0 and t4 and between the instants t5and t9 there is a so-called dead time phase during which both thecontrol voltage U_(G1) and the control voltage U_(G2) are equal to zeroand thus control voltages acting as switch-off control signals arepresent. The dead time phases T_(tot) are set such that a ZVS operationis possible. In the I(t) diagram the hatched areas represent a measurefor the energy available for charging/discharging the capacitance Cp. Inthe case shown in FIG. 3 the available energy is enough.

[0031] The operating state shown by waveforms in FIG. 3 represents, forexample, a case of inductive load i.e. the current I lags relative tothe first harmonic of the voltage U3. In such an operating state a ZVSoperation (Zero Voltage Switching) of the converter 1 is possible.

[0032]FIG. 4 shows in contrast respective waveforms by way of examplefor a case of capacitive load. In such an operating state the current Ileads relative to the first harmonic of the voltage U3. In the case of acapacitive load a ZVS operation of the converter 1 is no longerpossible. At the instant t0 in FIG. 4 the circuit element S2 is switchedoff. The current I is then positive, so that a gradual charging on thecapacitance Cp up to the voltage U1 (as is the case in FIG. 3 betweenthe instants t1 and t2) is impossible because of the current Icontinuously being transferred by the energy stored in the inductanceLr. In that case, the voltage U3 is abruptly increased from the zerovalue to the value U1 at the instant t4 at which the circuit element S1is switched on, that is to say, the full voltage U1 is still applied tothis circuit element when S1 is switched on. Accordingly, switching thecircuit element S2 on in the case of a capacitive load is not effectedwithout any voltage, because at instant t9, at which the circuit elementS2 is switched on, the voltage U3 still has the value U1 and abruptlyfalls to the zero value. Since in the case of the capacitive load, highswitching losses (correspondingly large values for the product from thecurrent I and the circuit element voltages U_(S1) and U_(S2)respectively, at the instants t4 and t9) develop in the circuit elementsS1 and S2 arranged here as MOSFET transistors, which losses may evenlead to the circuit elements being destroyed, this operating state is tobe avoided. How this happens will be further explained hereinafter withreference to FIG. 7.

[0033]FIG. 5 shows as a block diagram the basic structure of the controlcircuit 10 used for controlling the circuit element S1. A function block11 combines the measuring and evaluation unit which transfers during thedead time phases T_(tot) which lie immediately before the switch-onphases T_(ton)(S1) of the circuit element S1, the measured voltageU_(S1) or a signal equivalent to this voltage to a comparator device 12,which compares this applied signal with a first threshold U_(th1). Whenthe first threshold is reached, a set signal corresponding to a logic“one” is applied to an OR gate 13.

[0034] The control circuit 10 further includes circuit elements combinedby a function block 14, which circuit elements determine differentialquotients of the circuit element voltage U_(S1) present during the deadtime phases T_(tot) immediately preceding the switch-on phasesT_(on)(S1) and apply this voltage to a second comparator device 15 whichcompares the differential quotients dU_(S1)/dt with a second thresholdU_(th2). When the second threshold U_(th2) is reached, a set signalcorresponding to a logic “one” is applied to the OR gate 13.

[0035] In addition, the control circuit 10 includes a timer 16 whichstarts at the beginning of a dead time phase T_(tot), which immediatelyprecedes a switch-on phase T_(on)(S1) and applies a corresponding timesignal to a comparator device 17 which compares this applied time signalwith a predefinable maximum permissible dead time phase lengthT_(tot,max). When this maximum dead time phase length is reached, thecomparator device 17 applies a set signal that corresponds to a logic“one” to the OR gate 13.

[0036] If the output of the OR gate 13 produces a logic “one”, thiseffects the beginning of a switch-on phase T_(on)(S1) or the end of therespective previous dead time phase T_(tot). If there is a logic “one”on the output of the OR gate 13, the timer 16 is reset and circuit meanscombined by a function block 18 provide for a predefinable switch-onphase T_(on)(S1) that the control signal U_(G1) acting as a switch-onsignal is applied to the control input of the circuit element S1.Furthermore, the function block 18 combines switching means whichactivate the measuring and evaluation devices in the function blocks 11and 14 and the timer 16 after a switch-on phase T_(on)(S2) has ended. Arespective activating signal, which is used as an enable signal for themeasuring and evaluation devices of the function blocks 11 and 14 and asa trigger signal for the timer, is applied by the function block 18 tothe respective function blocks 11, 14 and 16 at that instant. Thishappens at the instant at which a signal 19 is applied to the functionblock 18 at the end of a switch-on phase T_(on)(S2), which signal 19 isgenerated by a second control circuit 10′ which is used for controllingthe circuit element and is arranged similarly to the control circuit 10.Accordingly, at the end of a switch-on phase T_(on)(S1), also thefunction block 18 or the control circuit 10 respectively, generatessignal 20 for the corresponding second control circuit 10′.

[0037]FIG. 6 shows a transmission function A(s) which expresses thepattern of the quotient U2/U3 as a function of the frequency f. At theresonant frequency f_(r) of the converter 1, which frequency isdetermined, in essence, by the capacitance Cr and the inductance Lr, thetransmission function A(f) has its maximum. At frequencies f lower thanf_(r)(area I) there is a capacitive load. Frequencies higher thanf_(r)(area II) on the other hand correspond to converter modes ofoperation with an inductive converter load. At frequencies f above theresonant frequency f_(r) the converter can accordingly be used. FromFIG. 6 is apparent that the capacitive mode of operation (area I) is tobe avoided also because the customarily used control mechanisms are nolonger effective for controlling the converter output voltage U2. For inthe area I, contrary to the area II, the value of A(f) diminishes with adiminishing frequency, so that instead of a negative feedback like inarea I (rising value of A(f) with a falling frequency f), there is apositive feedback, which prevents a control of the output voltage U2.

[0038] The flow chart shown in FIG. 7 shows how the control unit 4monitors (by means of circuit arrangements not further shown) whether aninductive load or a capacitive load occurs when the converter 1 is used.The monitoring is preferably effected cycle by cycle to ensure ascontinuous a monitoring as possible. Block 30 represents one of thesuccessive switch-on phases (T_(on)(S1) or T_(on)(S2)) of the circuitelements S1 and S2. At the end of each dead time phase T_(tot)represented by block 31 and following a switch-on phase a test is madewhether the voltage on the one of the two circuit elements that is to beswitched on next is smaller than a predefinable threshold U_(th). Withthe converter 1 shown in FIG. 2, the two switching voltages U_(S1) andU_(S2)(=U3) are measured. The switching voltage U_(S1), however, couldalso be indirectly derived from the voltage U1 and from the voltageU_(S2) or U3 respectively as a difference U1−U3. The threshold isselected such that it lies between the forward voltage of the diodes D1and D2 and the value of the voltage U1, because in case of an inductiveload the voltage on the circuit elements S1 and S2 when the circuitelements are switched on is equal to the diode forward voltage of therespective parallel-arranged diode (see FIG. 3) and in the case of acapacitive load the respective switch-on voltage of the circuit elementis equal to the value of the voltage U1. If in the step represented byblock 32 it is established that the respective circuit element voltageis smaller than the threshold U_(th) (branch Y), the converter mode iscontinued with the next switch-on phase T_(on)(block 30). If in thisstep, however, it is established that the respective circuit elementvoltage exceeds a threshold U_(th)(branch N), which corresponds to thecase of a capacitive load, the normal operation of the converter isbroken off and a new starting sequence of the converter is carried outin normal fashion (block 33).

[0039]FIG. 8 shows as a block diagram the basic structure of a secondembodiment of the control circuit 10 used for controlling the circuitelement S1. A function block 11 combines the measuring and evaluationunit which transfers during the dead time phases T_(tot) which lieimmediately before the switch-on phases T_(ton)(S1) of the circuitelement S1, the measured voltage U_(S1) or a signal equivalent to thisvoltage to a comparator device 12, which compares this applied signalwith a first threshold U_(th1). When the first threshold is reached, aset signal corresponding to a logic “one” is applied to an OR gate 13.

[0040] In addition, the control circuit 10 includes a timer 16 whichstarts at the beginning of a dead time phase T_(tot), which immediatelyprecedes a switch-on phase T_(on)(S1) and applies a corresponding timesignal to a comparator device 17 which compares this applied time signalwith a predefinable maximum permissible dead time phase lengthT_(tot,max). When this maximum dead time phase length is reached, thecomparator device 17 applies a set signal that corresponds to a logic“one” to the OR gate 13.

[0041] If the output of the OR gate 13 produces a logic “one”, thiseffects the beginning of a switch-on phase T_(on)(S1) or the end of therespective previous dead time phase T_(tot). If there is a logic “one”on the output of the OR gate 13, the timer 16 is reset and circuit meanscombined by a function block 18 provide for a predefinable switch-onphase T_(on)(S1) that the control signal U_(G1) acting as a switch-onsignal is applied to the control input of the circuit element S1.Furthermore, the function block 18 combines switching means whichactivate the measuring and evaluation devices in the function blocks 11and 14 and the timer 16 after a switch-on phase T_(on)(S2) has ended. Arespective activating signal, which is used as an enable signal for themeasuring and evaluation devices of the function blocks 11 and 14 and asa trigger signal for the timer, is applied by the function block 18 tothe respective function blocks 11, 14 and 16 at that instant. Thishappens at the instant at which a signal 19 is applied to the functionblock 18 at the end of a switch-on phase T_(on)(S2), which signal 19 isgenerated by a second control circuit 10′ which is used for controllingthe circuit element and is arranged similarly to the control circuit 10.Accordingly, at the end of a switch-on phase T_(on)(S1), also thefunction block 18 or the control circuit 10 respectively, generatessignal 20 for the corresponding second control circuit 10′.

[0042]FIG. 9 shows a transmission function A(s) which expresses thepattern of the quotient U2/U3 as a function of the frequency f. At theresonant frequency f_(r) of the converter 1, which frequency isdetermined, in essence, by the capacitance Cr and the inductance Lr, thetransmission function A(f) has its maximum. At frequencies f lower thanf_(r)(area I) there is a capacitive load. Frequencies higher thanf_(r)(area II) on the other hand correspond to converter modes ofoperation with an inductive converter load. At frequencies f above theresonant frequency f_(r) the converter can accordingly be used. FromFIG. 6 is apparent that the capacitive mode of operation (area I) is tobe avoided also because the customarily used control mechanisms are nolonger effective for controlling the converter output voltage U2. For inthe area I, contrary to the area II, the value of A(f) diminishes with adiminishing frequency, so that instead of a negative feedback like inarea I (rising value of A(f) with a falling frequency f), there is apositive feedback, which prevents a control of the output voltage U2.

[0043] The flow chart shown in FIG. 10 shows how the control unit 4monitors (by means of circuit arrangements not further shown) whether aninductive load or a capacitive load occurs when the converter 1 is used.The monitoring is preferably effected cycle by cycle to ensure ascontinuous a monitoring as possible. Block 30 represents one of thesuccessive switch-on phases (T_(on)(S1) or T_(on)(S2)) of the circuitelements S1 and S2. During a dead time phase T_(tot) shown by block 31the derived value (differential quotient) of the voltage present on acircuit element, more particularly for each dead time phase andaccordingly for each renewed switching on of a circuit element S1 or S2.From FIGS. 3 and 4 it becomes apparent that with an inductive load (FIG.3) the pattern of this derived value deviates from the pattern with acapacitive load (FIG. 4) during the time spaces in the dead time phasesin which both circuit elements S1 and S2 are non-conducting (i.e. herein the time spaces, for example, from t0 to t4 and from t5 to t9). Thisis used for detecting whether an inductive or a capacitive load ispresent. The threshold U_(th) is accordingly set to a value from therange between the derived voltage values to be expected of the circuitelements for inductive or capacitive load respectively, during thesetime spaces.

[0044] Particularly the characteristic fall or rise respectively of thevoltage U3 can be used in the time spaces between t0 and t1 or betweent5 and t6 respectively (and the respective preceding and following timespaces) in the case of the capacitive load (FIG. 4). This leads to avery fast detection of the type of load. Another possibility consists ofevaluating the characteristic rise or fall respectively of the voltageU3 in the time spaces between t1 and t2 or between t6 and t7respectively (and the respective preceding and following time spaces)that occurs with an inductive load (FIG. 3).

[0045] To counteract erroneous measurement results due to high frequencyvoltage components, the measured derived value is also low-pass filteredwhile the time constant of the filter is to be low compared to thelength of the dead time phase.

[0046] Alternatively, in lieu of the direct comparison of the derivedvalue of circuit element voltages with a threshold U_(th), there couldalso be made a comparison of a threshold U_(th) with a time-averagevalue of the respective switch element voltage in dead time phases. Theformation of an average value is linked with a signal smoothing. Moreparticularly the average value is evaluated for the time spaces betweent1 and t2 and between t6 and t7 respectively (and the respectivepreceding and following time spaces). The average value, however, couldalso be formed for respective segments of these time spaces.

[0047] With the converter 1 shown in FIG. 2 the two switching voltagesU_(S1) and U_(S2) (=U3) are evaluated. The switching voltage U_(S1),however, could also be determined indirectly from the voltage U1 and thevoltage U_(S2)=U3 as a difference U1−U3.

[0048] If in the step represented in block 32 it is established that therespective switch element voltage is smaller than the thresholdU_(th)(branch Y), the converter mode is continued with the nextswitch-on phase T_(on)(block 30). If in this step, however, it isestablished that the respective switch element voltage exceeds thethreshold U_(th)(branch M), which correspond to the case of capacitiveload, the normal operation of the converter is terminated and the newstarting sequence of the converter is carried out in normal fashion(block 33).

1. A converter comprising circuit elements (S1, S2) for chopping a DC voltage (U1), in which switch-on phases of the circuit elements (S1, S2) are alternating, and comprising a circuit assembly (5) with resonant circuit elements (Cr, Lr) which is used for processing the chopped DC voltage (U3) and for producing an output voltage (U2), characterized in that in a dead time phase (T_(tot)) before a circuit element is switched on, the voltage (U_(S1), U_(S2) respectively) present on the circuit element is compared with a threshold (U_(th)) and from the comparison result there is ascertained whether an inductive or capacitive converter load is present.
 2. A converter as claimed in claim 1, characterized in that the comparison with the threshold is made in each dead time phase (T_(tot)) before either of the circuit elements (S1 or S2 respectively) is switched on.
 3. A control unit (4), more particularly an integrated circuit, for controlling at least one of the circuit elements (S1, S2) of a converter (1) which are used for chopping a direct voltage (U1), in which converter switch-on phases of the circuit elements (S1, S2) are alternating and which converter includes a circuit assembly (5) with resonant circuit elements (Cr, Lr) which is used for processing the chopped direct voltage (U3) and for producing an output voltage (U2), characterized in that the control unit (4) is provided for comparing in a dead time phase (T_(tot)) before the circuit element is switched on the voltage (U_(S1) or U_(S2) respectively) present on the circuit element with a threshold (U_(th)) and ascertaining from the comparison result whether an inductive or capacitive converter load occurs.
 4. A converter comprising circuit elements (S1, S2) for chopping a DC voltage (U1), in which switch-on phases of the circuit elements (S1, S2) are alternating, and comprising a circuit assembly (5) with resonant circuit elements (Cr, Lr) which is used for processing the chopped DC voltage (U3) and for producing an output voltage (U2), characterized in that during a dead time phase (T_(tot)) the derived value (dU_(S1)/dt) of the voltage (U_(S1)) present on a circuit element is determined and with the aid of the determined derived value (dU_(S1)/dt) there is ascertained whether an inductive or a capacitive converter load is present.
 5. A converter as claimed in claim 4, characterized in that the determined derived value (dU_(S1)/dt) is compared with a threshold (U_(th)) by means of a comparator (15) and from the comparison result there is ascertained whether an inductive or capacitive converter load is present.
 6. A converter as claimed in claim 4, characterized in that during a dead time phase (T_(tot)) a time-average value is determined for the derived value (dU_(S1)/dt) of the voltage (U_(S1)) present on a circuit element and a comparison with a threshold (U_(th)) is made by means of a comparator (15) and from the result there is ascertained whether an inductive or capacitive converter load is present.
 7. A converter as claimed in claim 5 or 6, characterized in that the comparison with the threshold (U_(th)) is made each time before either of the circuit elements (S1, S2 respectively) is switched on.
 8. A control unit (4), more particularly an integrated circuit, for controlling at least one of the circuit elements (S1, S2) of a converter (1) which are used for chopping a DC voltage (U1), in which converter the switch-on phases of the circuit elements (S1, S2) are alternating and which converter comprises a circuit assembly (5) with resonant circuit elements (Cr, Lr) which assembly is used for processing the chopped DC voltage (U3) and for producing an output voltage (U2), characterized in that the control unit (4) is provided for determining during a dead time phase (T_(tot)) the derived value (dU_(S1)/dt) of the voltage (U_(S1)) present on a circuit element and with the aid of the determined derived value (dU_(S1)/dt) ascertaining whether an inductive or capacitive converter load is present. 